The semiconductor industry is continuously reducing the dimensions of devices. In Back End Of Line (BEOL) processing, there is an interest in reducing dimensions of conductive layers as well as in the separation of the different conductive structures from each other. Isolation of these structures therefore becomes extremely important, and low-k materials are used to replace conventional dielectric insulating materials. The trend is to move on to the incorporation of air, namely, so-called “air regions” or “airgaps”, as an isolation material for conductive structures.
Examples of airgaps incorporated in BEOL structures include those based on the removal of a sacrificial material through a porous capping layer. The sacrificial material is evaporated through the porous capping layer and sealed afterwards by deposition of an extra layer. Examples of these methods are described in U.S. Pat. No. 6,165,890 and U.S. Pat. No. 6,287,979.
In Front End Of Line (FEOL) processing, isolation of the active device areas is one of the critical issues when dimensions are reduced. The device isolation methodology has been changed or modified several times with the aim of enhancing density or device functionality. Many of the methods had certain process limitations and were not very scalable. The introduction of “trench isolation technology” has been accepted quickly by industry as the primary isolation technique for advanced device and circuit designs (see, e.g., U.S. Pat. No. 4,104,086).
For bipolar or BiCMOS technologies, device isolation is of particular importance, because the collector nodes, which are buried in the substrate, carry active signals. This is in contrast to MOS transistors, where the wells do not carry active signals. The collectors are isolated from the substrate by collector-substrate pn junctions. This junction has a box-like shape with a bottom surface determined by the transistor area and a lateral surface determined by both the transistor perimeter and the n-type region depth. It introduces a parasitic junction capacitance at the collector terminal. The value of the parasitic junction capacitance is given by the sum of a perimeter term, associated with the lateral junction, and an area term, associated with the bottom junction.
Deep trench isolation structures are employed in conventional systems, and are commonly used in advanced bipolar technologies in order to reduce the total device area and the collector to substrate parasitic capacitance. The introduction of a deep trench filled with an insulator adjacent to the bipolar transistor replaces the lateral junction with a silicon-insulator-silicon capacitor, and it can be used to reduce the value of the perimeter component of the capacitance. As the transistor dimensions are scaled down, the total value of the capacitance is also effectively reduced, because the percent weight of the perimeter component increases.
The reduction of the collector-substrate capacitance allows further optimization of the high-speed or low-power performance of bipolar transistors. In common-emitter stages designed in a low-power bipolar technology, the collector-substrate capacitance is a significant contributor to the total switching delay. A low collector-substrate capacitance value helps to produce state-of-the-art power-delay products. Other applications that can benefit from the introduction of deep trench isolation include, for example, high voltage applications that achieve high breakdown voltage. Deep trench isolation can also be employed to isolate high voltage regions from low voltage regions in applications where good latch-up immunity or low substrate noise is desired.
In a full BiCMOS technology, the deep trench has to be etched, refilled, and planarized with a CMOS compatible process module. This fact imposes constraints on the selection of the process steps and on the location of the module in the complete process flow. The trench isolation technology is based on four key process elements: trench formation; trench lining; trench filling; and trench planarization. In particular, the choice of the filling material is very important, as it determines the value of the actual capacitance of the collector substrate perimeter component. LOW-κ materials are desired, with silicon dioxide being the most straightforward candidate. Although a complete oxide filling is preferred, because of its good isolation properties and low dielectric constant, this scheme is not easy to implement for several reasons. Namely, it is difficult to obtain a complete fill of the deep trench without leaving any voids, and also because a completely oxide-filled deep trench would generate localized stresses and defects during and after processing.
For these reasons, a state-of-the-art deep trench module often consists of a combined oxide/polysilicon filling. The polysilicon material makes it easier to fill the trench properly and thermal stress is reduced because the thermal expansion coefficient of polysilicon and the silicon substrate match much better. However, the isolation qualities are less (i.e., the κ-value of polysilicon is roughly a factor of 3 higher than that of oxide). For that reason, it is beneficial to increase the oxide/polysilicon ratio as much as possible, as this will reduce the final collector to substrate perimeter capacitance. One of the ways to accomplish this in a modern CMOS technology with a shallow trench isolation scheme is by the introduction of the deep trench isolation prior to the shallow trench isolation. In this way, the thickness of the oxide liner in the deep trench can be well balanced with respect to possible stress generation, thereby obtaining a low perimeter capacitance value without affecting the CMOS shallow trench isolation module itself.
Alternatively, as described by Washio et al. (IEEE Transactions on Electronic devices, Vol. 48, 2001), double deep trenches can be used, at the expense of increased device area.